TSMC latest process nodes and advanced chip packaging technology

Source:   Editor: admin Update Time :2019-09-04

After the 2019 VLSI seminar in Japan, TSMC held a small press conference. Introducing the latest process and packaging technology, below is the details:


N7
TSMC believes that their 7-nanometer node (N7) is the most advanced logic technology so far. At the recent VSLI workshop, TSMC co-authored a paper on their 7nm node. Except a few major customers, most TSMC customers are said to have switched directly from 16nm to 7nm. The N10 node is considered to be a short-lived node and is mainly used for production learning. When switching from N16 to N7, N7 can provide 3.3 times gate grid density and about 35-40% speed boost or 65% low power compared with 16nm.


A key highlight of the 7nm process is its defect density. TSMC said that learning from the 10nm node, the N7 D0’s defection density reduction is the fastest in history and can smooth to a considerable level compared with previous nodes. As the company joined HPC, they began reporting defect density for mobile customers and HPC customers, the chip size is of 250 square millimeters and larger.


Learning from the N10 node, the N7 D0’s reduction ramp is the fastest in history and can level with previous nodes. As the company entered the field of high-performance computing, they began reporting defect density for mobile customers and high-performance computing customers with die sizes of 250 square millimeters and above.


TSMC's demand for its 7-nanometer node has declined slightly in the past six months, with a ring ratio of about 1%. The vast majority of revenue continues to come from their very mature 16-nm node. However, wafer shipments increased slightly in the second quarter and are expected to occur in the second quarter. When comparing the longer trends, this is actually the lowest volume in the second quarter in three years. Despite this, they believe that the revenue from N7 will reach 25% of the total revenue this year.


TSMC's demand for its 7-nanometer node has declined slightly in the past six months, with a ring ratio of about 1%. The vast majority of revenue continues to come from their very mature 16-nm node. However, wafer shipments increased slightly in the second quarter and are expected to occur in the second quarter. When comparing the longer trends, this is actually the lowest volume in the second quarter in three years. Despite this, they believe that the revenue from N7 will reach 25% of the total revenue this year.

 

Technology nodes by percent of revenue, WikiChip analysis


TSMC wafer shipment


N7P
TSMC has released an optimized version of the N7 process called N7 Performance Plus (N7P). N7P should not be confused with N7+. N7P is an optimized DUV-based process that uses the same design rules and is fully IP compatible with the N7. N7P introduces FEOL and MOL optimizations, which are said to increase performance by 7% at equal power or 10% at equal speed.


N7+
TSMC's N7+ is the first process technology to use EUV at several key layers. N7+ entered the mass production phase last quarter (the second quarter). TSMC said that the N7+’s output is comparable to that of the N7. Compared with the N7 process, the density of N7+ has increased by about 1.2 times. It is said that the performance of the N7+ can increase by 10% at the same power, or save power by 15% at the same performance level. Based on paper, the N7+ seems to be slightly better than the N7P. But keep in mind, these improvements can only be obtained with new physical re-implementation and new EUV masks.


N6
N6 plans to use more EUV layers than N7+. This complies with the design rule and make N6 IP compatible with N7, so that this can be the primary migration path for most customers. The N6 design can be re-implemented or improved on the N6 using EUV masks and fidelity to take advantage of polymer diffusion edge (PODE) and continuous diffusion (CNOD) standard cell abutment rules, which are said to give an additional 18% density improvement. It is worth emphasizing that the N6 is unique in that it will actually enter venture production early next year and peak before the end of 2020. TSMC said: N6 is an improvement based on the lessons of N7+ and N5 EUV.


N5
TSMC's 5nm process is the next "full node" after N7. N5 entered the risk production trial phase in the first quarter of this year and is expected to accelerate in the first half of 2020. N5 uses EUV extensively on "multilayer". TSMC has already shown very high yields, and in terms of D0, they are similar to the development trajectory of the N7 production process. As a long-standing node, the N5 program is expected to grow faster than N7 in terms of revenue.
Compared with the N7, the N5 provides 1.8 times logic density. In terms of performance, under same power level, N5’s performance increased by 15%, and the power consumption can reduce by 30% under the same performance level. Like the N7, the N5 will come in two types - mobile customers and high performance computing (HPC). HPC offers additional options for the unit, with a 25% performance improvement over the N7.


N5P
Like their 7-nanometer process, TSMC will offer an optimized version of its N5 process called the N5 Performance Plus (N5P). This process uses the same design rules and is fully IP compatible with the N5. Optimized by FEOL and MOL, the N5P is 7% better than the N5 at equal power level and can save 15% power under the same level of performance. The time schedule for N5P is a bit fuzzy at the moment, but TSMC hints that mass production will be available by the end of 2020 or early 2021.


N3
TSMC said that their 3nm process is progressing smoothly. N3 is expected to be launched around 2022. Although TSMC has previously talked about GAA as a potential successor to FinFET, both TSMC and Intel are proving that FinFET, which is now easier to manufacture, can expend well in terms of performance. Another node. We currently believe that TSMC may continue to use FinFET as its N3, but will move to GAA in subsequent nodes.



Next package generation
As the complexity and cost of leading edge nodes increase, the demand for chip-based solutions continue to grow. The three main reasons are to divide the die into smaller chips, using older, mature modules and nodes from other parts of the SoC. These nodes do not necessarily scale well and implement higher systems integration through components such as HBM.


TSMC offers a number of technologies as part of its Wafer Level System Integration (WLSI) platform, which covers everything from low idle mobile applications to high performance computing. Their chip-wafer-substrate (CoWoS) packages target at artificial intelligence, network and high-performance computing applications, while their integrated fan-out (InFo) packages target at network and mobile applications.


The TSMC InFO package is their general fan-out wafer level package (FOWLP) solution, with many different styles depending on the application. InFO uses dense RDL and fine pitch through the package vias (TSMC also use InFO vias or TIVs). They are integrated on the substrate for fan-out (InFO_oS), InFO (MS) with substrate memory and InFO Ultra High Density (InFO_UHD), applicable for any device from high-performance mobile devices to networking and HPC applications.


Especially for 5G mobile platforms, TSMC has InFO POP (InFO_POP) for mobile applications, InFO Antenna-in-package (InFO_AiP) for RF front-end module (FEM) applications and Multi-stack (MUST) for RF front-end. Baseband modem.


3D-MiM for higher bandwidth
One of the earliest examples of InFO_POP was the Apple A10 released in 2016 (previous processors had regular POP). However, even the InFO_POP has disadvantage caused by of limited memory bandwidth due to controller and TIV tones. This problem is further exacerbated by the upcoming 5G and AI edge/mobile applications are essentially more memory bandwidth limited. To overcome this problem, TSMC announced 3D-MUST-in-MUST packaging technology (please note that MUST stands for multi-stacking). 3D-MiM is integrated by fan-out (InFO) WLS integration using high-density RDL and fine-pitch TIV, they integrated and formed multiple vertically stacked memory chips. As you might imagine, I/O must be exposed on one side of the chip, and these chips are independently connected to the SoC to form a wide I/O interface.


TSMC demonstrated SoC technology with 16 memory chips in a single package. The chip has a footprint of 15 mm x 15 mm and a height of only 0.55 mm. Compared to a flip chip POP package, the chip has twice memory bandwidth at half of the height.

Since there are no substrates and no bumps, the distance from memory I/O to SoC is much shorter, thus it has better electrical performance characteristics. In addition, a thinner form is said to provide better heat dissipation.


By the way, 3D-MiM is not limited to a single SoC. In fact, TSMC talked about using multiple SoCs and a large amount of memory chips (for example, 2 SoCs with 32 memory chips) to create HPC applications with high bandwidth and low power as an alternative technology to current 2.5D (eg HBM). A key difference here is that the InFO memory chips are directly connected to the SoC without the need for a basic logic chip.


InFO packaged antenna (InFO_AiP)
TSMC has developed the InFO antenna package (InFO_AiP) specifically for 5G millimeter wave system integration. The package attempts to solve the link or interconnection between the actual chip and the antenna, which can result in severe transmission loss. TSMC does this through the slot-coupled patch implemented in the RDL and the embedded RF chip in the molding compound itself, the chip is directly interconnected to the RDL without bumps.
Since the performance of the interconnection between the antenna and the chip is a function of surface roughness and the transition between the chip and the package, the InFO material and RDL uniformity allow for lower transmission losses. Compared with flip-chip AiP, TSMC claims that it can improve performance by 15%, thermal resistance reduced by 15%, and both reduced by 30%.


Network and high-performance computing
For high performance computing and networking applications, TSMC provides CoWoS and InFO on the baseboard and memory (_oS / _MS). CoWoS can be extended to 2 reticle with an aggressive line/pitch of 0.4μm/0.4μm. This is a very mature technology with very high yields and has been massively produced for over five years. CoWoS has been widely used in GPUs, but can also be found in a variety of network applications. TSMC said that they have more than 15 tapeout so far.


Currently, CoWoS supports 6 HBM2 modules with a speed of 1.5 TB/s. TSMC reports are researching for higher bandwidth solutions and larger silicon areas with more than three reticles.


For network applications, TSMC provides InFO on the substrate, which can achieve an integrated Si region with up to 1 reticle, but with a slightly looser L/S spacing of 1.5μm/1.5μm. The current technology has a minimum I/O pitch of 40μm and a minimum C4 bump pitch of 130μm. The production of InFO_oS began to grow in the second quarter of 2018. They are currently working to achieve integration of more than two chips and silicon area with 1.5x reticle size.


As for AI applications and similar applications, TSMC's InFO memory substrate is designed to integrate with HBM. This technology currently has an RDL L/S of 2μm/2μm and is limited to a single reticle. In many ways, TSMC's charge to InFO_MS is an alternative to the performance cost sensitivity of CoWoS.


InFO Ultra High Density Package (InFO_UHD)
The two key parameters of drive performance and power are writing density and bump spacing. This is the goal behind the InFO ultra-high-density package. It has been reported that TSMC has reported 0.8/0.8μmL/s at 500 lines/mm and has over 10,000/mm2.


Integrated System Chip (SoIC)
SoIC is TSMC's next-generation "real" 3D packaging technology. SoIC is a chip-on-chip (CoW) stacking method that allows the mix and match of many different KGDs and even stack KGDs to be integrated - different in size and process nodes. It is both face-to-face and back-to-back technology, but looks like any other standard chip from the outside. You can actually combine SoIC with existing technologies (such as InFO, CoWoS or flip chip) in the same package. Like InFO_UHD, it currently has 10,000/mm2 bonds, and with the introduction of "SoIC +", they can eventually reach 1 million/mm2.

 


 

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