Why is the gap between MLC and SLC SSD so big, although they belong to NAND Flash technology?

Source:   Editor: admin Update Time :2019-08-02

Until now, the development of NAND flash technology has followed the trajectory of traditional memory technology, such as SRAM, DRAM, EEPROM and so on, storing a binary data in each memory cell. However, this type of NAND flash technology is now called Single Level Cell or SLC.

As time goes on, in order to pursue higher density and lower cost, a new type of flash cell has emerged, which can store multiple binary data in each memory cell. This type of NAND flash is called Multi Level Cell or MLC, and each cell can store two bits. There are also exiting new NAND flash named Triple Level Cell or TLC on the market, storing three bits in each cell. But the durability of TLC is extremely low, and the P/E cycle is about 300. Therefore, even with the help of controller and firmware technology, TLC NAND is not suitable for industrial applications.

Therefore, we will focus on the key differences between SLC and MLC NAND in this article, as well as the technical key points of these two types of NAND.

Density and cost per Bit
MLC NAND flash memory stores 2 bits of data in each cell. This higher storage density means that when faced with the same amount of data, the storage physical size of MLC device is smaller than that of SLC device. The smaller storage physical size is equal to smaller Die size, so the cost per bit in MLC NAND flash is lower.
However, the advantage of MLC device is not twice that of SLC. The reason is that MLC device requires more complex programs and read circuits, which causes these circuits to consume more Die space.

Device-level performance
In order to store two bits of data in a MLC NAND flash memory cell, the programmable circuit must be able to place four precise charges on the device's floating door or use a voltage threshold window equivalent to the SLC device. Figure 1 shows the Vt distribution of SLC and MLC.

A more complex and time-consuming programming algorithm is needed to accurately distribute charge to the floating gate of Flash device. Therefore, the programming time of MLC NAND Flash is four times longer than that of SLC NAND Flash.
Such similar performance penalty also exists for read operations, because it takes a long time for the read-aware circuit to accurately distinguish the four states. As a result, the read time of MLC NAND Flash is three times longer than that of SLC NAND.

System-level performance
In addition to the basic device-level performance deficiencies mentioned above, MLC NAND Flash also suffers from lower system-level performance due to a lack of support for some system features, such as Copyback programming and Partial programming.

Copyback programming allows users to move a page of data from one location to another in a flash device without having to transfer data to memory or copy it out of memory. In terms of a 2K Byte/page NAND Flash device, copyback programming saves more than 170us per page. Copyback programming is most effective for wear leveling, read, write, and update operations.

Partial programming allows users to program only a portion of the data in the device. For a 2K Byte/page NAND Flash, a page of data contains four data sectors in typical PC application programming. Partial programming allows users to write data for one sector at a time, which is very useful for read, modify, write operations or for small data transfers.

Because of its unique structure and device characteristics, MLC NAND Flash is more sensitive to interference, when accessing part of an array may interfere with other parts of the same array. Therefore, in order to minimize the possibility of array interference, MLC NAND Flash manufacturers do not select or allow partial programming or copyback programming. However, a lack of these two features means that MLC NAND Flash slows down when users need to move data from one location of the device to another, and that MLC NAND Flash performs worse than SLC NAND Flash in small block operations.

The programming of NAND flash memory (P/E operation) can cause damage to the physical oxide layer (thin oxide layer separates the floating gate from the substrate). This kind of damage is accumulating slowly during the daily reading and writing process in Flash. As a result, with the number of programming times (P/E) increases, the number of erase cycle will increase continuously, which will cause the voltage threshold window to narrow, shift, or shrink. Voltage threshold is to determine the programming and erase state. When the displacement of erase voltage threshold exceeds the detection threshold, it will lead to the reading judgment error, as shown in Figure 2 (W/E Cycle and P/E Cycle).

MLC NAND Flash needs to maintain four different state data need in the same voltage threshold window. Its available threshold window is about 1/2 of SLC NAND Flash in size. That is, when the programming mechanism and oxide damage of MLC NAND are the same as that of SLC NAND, the program/erase threshold window of MLC NAND is only 1/2 of that of SLC NAND. It means that the erase window narrowing of MLC NAND Flash is earlier and more obvious than that of MLC NAND, as shown in Figure 3.

At present, SLC NAND Flash with 4X/3Xnm technology can support 70 thousands P/E Cycles at least, while MLC NAND Flash using 2X/1X/1Ynm technology provides about 3 thousands P/E Cycles. This is not just a magnitude difference in low endurance for MLC NAND Flash. As costs decline and the scalability continue to grow during the development of flash technology, this difference will only get larger. Figure 4 shows the change in endurance cycles and durability trends.

Lower durability constraints mean that MLC NAND Flash is not suitable for frequently updating data and corresponding applications or for scenarios where higher scalability is required to pursue higher reliability.

What is enterprise MLC?
With the aim of solving the problem of low durability of MLC NAND, the mainstream flash manufacturers provide so-called enterprise MLC (eMLC). This type of flash manufacturing process is the same as the standard MLC Flash. The difference between them is that enterprise MLC trades performance and durability better and provides a more reliable P/E algorithm. Compared with standard MLC, eMLC provides higher durability at the expense of lower performance. The reason for lower performance is that accurate programming algorithms are needed to ensure sufficient voltage threshold window to determine the programming state.

However, it is noteworthy that the durability of eMLC is less than half that of SLC NAND under the same technology node and state. Therefore, SLC NAND Flash is still recommended option for applications that require long-term durability.

Error Rates
As mentioned in the previous section, the voltage threshold window for each state of MLC NAND is much smaller than that of SLC NAND, which causes MLC NAND to be more prone to errors when being read or interfered. When the distribution of threshold voltage deviates beyond the detection threshold due to excessive repetition of P/E cycle or temperature variation, data judgment errors will occur.

Program disturb
Program disturb often occurs in programmed adjacent cells. When the adjacent cell is exposed to a voltage higher than the normal voltage, program disturb occurs, as illustratd in Figure 5.

MLC NAND Flash is sensitive to program disturb, the main reason for which is that its voltage threshold window for each state of data is relatively small.

Read disturb
Read disturb occurs between adjacent cells, when stray charges are coupled to floating gates of unselected coils. Read disturb is not as serious as write disturb. However, it will get worse, as Flash gets smaller and smaller. Figure 6 illustrates read disturb.

As Flash technology becomes more and more sophisticated, the endurance will become worse due to read and write disturb. Cell to cell coupling effect will contribute to disturb errors. Figure 7 shows flash technology node and cell to cell coupling trend.

Cactus Technologies uses SLC NAND with 4X/3Xnm technologies as an industrial product, while its mainstream MLC NAND currently uses 2Xnm technology. As can be seen from the above figure, the cell-to-cell coupling effect of 2Xnm NAND is 3 to 5 times higher than that of 4X/3Xnm NAND.
In industrial applications, it is also noteworthy that when the threshold voltage and temperature range are extended, the effects of cell-to-cell coupling, cell leakage and voltage threshold change will worsen.

Summary of Cactus
In the previous sections, we have discussed some key differences between SLC NAND and MLC NAND, and introduced how some key reliability parameters will be affected as Flash technology shrinks to a smaller geometric size. It is important to remember that although MLC NAND has some advantages in high density and low cost, it still has low performance, low durability and low reliability.

Cactus Technologies believes that only SLC NAND can provide the superior performance, durability and reliability required in an industrial environment. Therefore, industrial applications usually use SLC NAND.

The flash disk controller manufacturers are aware of these shortcomings, and then propose various adaptive algorithms to compensate. With the help of these advanced algorithms, the durability of MLC NAND technology can be increased to more than 10 times of the standard MLC NAND. This improvement may be sufficient for some applications. However, it is worth noting from Figure 4 that even with a 10-fold improvement, the endurance of 1X/1Y MLC NAND still has less than half that of 4X/3X SLC NAND.

According to Cactus Technologies, only SLC NAND provides the superior performance, durability and long-term reliability required to operate in an industrial environment. If you have more questions about this topic, I hope this white paper can help you better understand the key difference between SLC NAND and MLC NAND.


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