Intel Releases Six Major Technology Pillar Strategies: 10/7nm Process Plus 3D Package to Create a New Generation of CPU Cornerstone
In the two or three years before the mass production from 14nm to 10nm, Intel has shouldered huge pressure. But, the performance of Intel has still well and provides support for Intel. And, finally, in June this year, the 10nm process was mass-produced in advance and the 10th generation Core Ice Lake processor with 10nm process was introduced.
From 10nm processor, Intel delivered a new entrepreneurial strategy from focusing on PC-centered business into data-centered business. Intel points out that with the explosion of data and the deeper digging of data dividends, the digital economy with data as the key production material will flourish.
The generation in future is big data generation. According to the data from IDC, The global intelligent interconnected devices in 2025 will exceed 15 billion, generating 175ZB of data. Among them, there will 8 billion intelligent interconnected devices in China, generating 48.6ZB of data.
To cope with the data deluge, Intel releases innovations based on six technical pillars in parallel.
These six pillars are process and packaging, architecture, memory and storage, interconnection, security, and software. Intel aims to grow exponentially with these six pillars.
Among the six technological pillars of Intel, the most important one is advanced technology and packaging technology, which is the core technology of Intel. The first 10nm Ice Lake processor will be the foundation work of future Intel processors. The reason for this is that this generation of processors not only use 10nm technology, but also upgrade the brand-new CPU micro architecture Sunny Cove.
At last year's architecture day, Intel had released a new generation of CPU cores, including Treamont, Gracemont, and the yet to be named Next Mont for its low-power Atom processors. And, Core series will have Sunny Cove, Willow Cove and Golden Cove .
In the core of the Sunny Cove, Intel focuses on improving ST single-core performance, adding new instruction sets, such as DL Boost instructions for AI acceleration and improving CPU parallelism with more cores.
The next Willow Cove core architecture will optimize transistors and redesign the cache system while the next generation of Golden Cove core architecture will continue to enhance single-core performance, enhance AI performance, and innovate in networking, 5G and security.
For the 10nm Sunny Cove architecture, the new architecture makes its IPC performance significantly improved compared with the Skylake architecture currently used by core, up to 40 percent and an average increase of 18percent. Such IPC growth will never be teased by netizens again.
As for the processor, Intel has also planned to focus on 10nm Ice Lake this year and Tiger Lake in 2020, which is also 10nm process. But, it will also upgrade the CPU core architecture and use the more advanced Xe GPU architecture, which is expected to improve the game and computing performance.
These are mainly architectural changes discussed above and Intel is also preparing for the next step in chip technology. In the future, 10nm will generate three generations of processes -- 10nm, 10nm+ and 10nm++. However, 7nm will be on the market in 2021 at the soonest and two generations of improved processes -- 7nm+ and 7nm++ will also be derived.
Starting with Ice Lake which will be launched in 2019 with 10nm process and new Sunny Cove architecture, Intel's future CPU upgrades will go back to a Tick-Tock cycle with a new 7nm process after two years from 2021 and the next generation of CPU core architecture expected.
In addition to 10 nm and 7 nm technology advantage after 2 years, Intel also has a breakthrough in advanced packaging. With increasing future semiconductor process complexity, the industry needs more powerful and more flexible chips. Intel's Foveros 3D package can "mix and match" different technology patent modules with various memory chips and I/O configurations in the new product form.
The design idea of the Foveros package is the industry's first popular Chiplets technology, which enables products to be decomposed into smaller "chip combinations", where I/O, SRAM and power transmission circuits can be integrated on the base chip and high-performance logic "chip combinations" are stacked on top.
Foveros is just a small test of Intel's packaging technology. Recently, at SEMICON West conference, Intel introduced three new advanced chip packaging technologies and launched a series of new basic tools, including EMIB, Foveros technology combined with innovative applications, new omni-directional interconnection (ODI) technology and so on.
The six pillar technologies proposed by Intel will be the main driving force for Intel in the next 10 years and even in the next 50 years and are expected to drive exponential innovation, while manufacturing process and packaging are the most basic technologies for making chips. As Raja Koduri, senior vice President of Intel, said that there was a density improvement in the process and packaging technology and there was an improvement in Foveros technology. Advanced packaging technology was used to provide the optimal chip for each workload.